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1 ? fn6492.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2009. all rights reserved all other trademarks mentioned are the property of their respective owners. ISL3034E, isl3035e, isl3036e 4-channel and 6-channel high speed, auto-direction sensing logic level translators the ISL3034E, isl3035e, isl3036e 4- and 6-channel bi-directional, auto-direction sensing, level translators provide the required level shifti ng in multi-voltage systems at data transfer rates up to 100mbps. the auto-direction sensing feature makes the ISL3034E, isl3035e, isl3036e ideally suited for memory-c ard level translation (or for generic four to six channel level translation) especially if bit-by-bit direction control is desired. the v cc and v l supply voltages set the logic levels on either side of the device. logic signals present on the ic?s v l side appear as higher voltage logic signals on the ic?s v cc side and vice versa. the isl3035e features a clk_ ret output that returns the same clock signal applied to the clk_v l input, but with timing that mimics the data returning from the i/ov cc inputs. the ISL3034E, isl3035e, isl 3036e operate at full speed with external input drivers that s ource as little as 4ma output current. each i/o channel is pulled up to v cc or v l by an internal 30a current source, allowing the ISL3034E, isl3035e, isl3036e to be driven by either push-pull or open-drain drivers. the ISL3034E and isl3036e include an enable (en) input that when driven low places the ic into a low-power shutdown mode, with all i/o lines tri-stated. all versions feature an automatic shutdown mo de, that places the part in the same shutdown state when v cc is less than v l . the states of i/ov cc and i/ov l during shutdown are chosen by selecting the appropriate product (see table 1). the ISL3034E, isl3035e, isl3036e operate with v cc voltages from +2.2v to +3.6v and v l voltages from +1.35v to +3.2v, making them ideal for data transfer between low-voltage microcontrollers or asics and higher voltage components. features ? best-in-class esd protecti on: 15kv iec61000-4-2 esd protection on all input, output, and i/o lines ? 100mbps guaranteed data rate ? four (isl3036) or six (isl3034, isl3035) bi-directional channels ? auto-direction sensing eliminates direction control logic pins ? enable input (ISL3034E, isl3036e) for logic control of low power shdn mode ? clock return output (isl3035e) ? compatible with 4ma input drivers or larger ? +1.35v v l +3.2v and +2.2v v cc +3.6v supply voltage range ? pb-free (rohs compliant) ? 16ld tqfn (2.6mmx1.8mm), 16 ld tqfn (3mmx3mm), and 14 ld qfn (3.5mmx3.5mm) packages applications ? simplifies the interface between two logic ics operating at different supply voltages ? sd card and minisd card level translation ? mmc (multi media card) level translation ? memory stick card level translation typical operating circuit table 1. summary of features part number data rate (mbps) number of channels en pin? i/ov l shdn state i/ov cc shdn state ISL3034E 100 6 yes 16.5k to v l 16.5k to v cc isl3035e 100 6 no 75k to v l high impedance isl3036e 100 4 yes 16.5k to v l 16.5k to v cc v l v cc i/ov l i/ov l isl3035e clk_ret i/ov l i/ov l i/ov l gnd i/ov cc i/ov cc i/ov cc i/ov cc i/ov cc clk_v l clk_v cc dat3 dat2 dat1 dat0 cmd clock gnd gnd +3.3v sd card dat3 dat2 clock_in dat1 dat0 cmd clock +1.8v system controller 0.1f 0.1f +1.8v 1f +3.3v data sheet march 31, 2009
2 fn6492.0 march 31, 2009 ordering information part number part marking temp. range (c) package (pb-free) pkg. dwg. # ISL3034Eirtz (note 1) 34tz -40 to +85 16 ld tqfn l16.3x3a ISL3034Eirtz-t (notes 1, 3) 34tz -40 to +85 16 ld tqfn l16.3x3a ISL3034Eiruz-t (notes 2, 3) gae -40 to +85 16 ld tqfn l16.2.6x1.8a isl3035eirtz (note 1) 35tz -40 to +85 16 ld tqfn l16.3x3a isl3035eirtz-t (notes 1, 3) 35tz -40 to +85 16 ld tqfn l16.3x3a isl3035eiruz-t (notes 2, 3) gaf -40 to +85 16 ld tqfn l16.2.6x1.8a isl3036eirz-t (notes 1, 3) 36ez -40 to +85 14 ld qfn l14.3.5x3.5 isl3036eiruz-t (notes 2, 3) gak -40 to +85 16 ld tqfn l16.2.6x1.8a notes: 1. these intersil pb-free plastic packaged pr oducts employ special pb-free material sets , molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std- 020. 2. these intersil pb-free plastic packaged pr oducts employ special pb-free material se ts; molding compounds/die attach materials and nipdau plate - e4 termination finish, which is rohs compliant and comp atible with both snpb and pb-free soldering operations. intersi l pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. please refer to tb347 for de tails on reel specifications. pinouts ISL3034E (16 ld tqfn) top view ISL3034E (16 ld tqfn) top view 12 11 10 15 14 13 5 6 7 1 2 3 i/ov l 1 v l i/ov l 2 i/ov l 6 en i/ov l 5 i/ov cc 1 i/ov cc 6 gnd i/ov cc 2 i/ov cc 3 i/ov cc 4 4 i/ov l 3 8 i/ov cc 5 9 16 i/ov l 4 v cc thermal pad 12 11 10 9 16 15 14 13 5 6 7 8 1 2 3 4 i/ov l 1 v l i/ov l 2 i/ov l 3 i/ov l 6 en i/ov l 5 i/ov l 4 v cc i/ov cc 1 i/ov cc 6 gnd i/ov cc 2 i/ov cc 3 i/ov cc 4 i/ov cc 5 ISL3034E, isl3035e, isl3036e
3 fn6492.0 march 31, 2009 isl3035e (16 ld tqfn) top view isl3035e (16 ld tqfn) top view isl3036e (14 ld qfn) top view isl3036e (16 ld tqfn) top view pinouts (continued) 12 11 10 15 14 13 5 6 7 1 2 3 i/ov l 1 v l i/ov l 2 clk_v l clk_ret i/ov l 5 i/ov cc 1 clk_v cc gnd i/ov cc 2 i/ov cc 3 i/ov cc 4 thermal pad 4 i/ov l 3 8 i/ov cc 5 16 v cc 9 i/ov l 4 12 11 10 9 16 15 14 13 5 6 7 8 1 2 3 4 i/ov l 1 v l i/ov l 2 i/ov l 3 clk_v l clk_ret i/ov l 5 i/ov l 4 v cc i/ov cc 1 clk_v cc gnd i/ov cc 2 i/ov cc 3 i/ov cc 4 i/ov cc 5 2 4 5 1 i/ov l 1 i/ov l 2 i/ov l 3 i/ov l 4 v l v cc 14 3 12 10 9 11 7 8 i/ov cc 2 i/ov cc 3 i/ov cc 4 nc gnd en nc 6 13 i/ov cc 1 thermal pad 12 11 10 9 16 15 14 13 5 6 7 8 1 2 3 4 i/ov l 1 i/ov l 2 i/ov l 3 i/ov l 4 i/ov cc 1 i/ov cc 2 i/ov cc 3 i/ov cc 4 v l nc nc v cc gnd nc nc en pin descriptions name function notes v cc v cc power supply, +2.2v to +3.6v. decouple v cc to ground with a 0.1f capacitor. for normal operation, v cc > v l . v l v l logic supply, +1.35v to +3.2v. decouple v l to ground with a 0.1f capacitor. for normal operation, v cc > v l . gnd ground pin en 15kv iec61000 esd protected enable input. logic ?0? puts the device in shutdown. logic ?1? enables the device. ISL3034E and isl3036e only i/ov cc x 15kv iec61000 esd protected input/output channel referenced to v cc . clk_v cc 15kv iec61000 esd protected input/o utput clock channel referenced to v cc . isl3035e only i/ov l x 15kv iec61000 esd protected input/output channel referenced to v l . clk_v l iec61000 esd protected input clock channel referenced to v l . isl3035e only clk_ret iec61000 esd protected output clock channel referenced to v l . isl3035e only ISL3034E, isl3035e, isl3036e
4 fn6492.0 march 31, 2009 absolute maximum rati ngs thermal information (all voltages referenced to gnd.) v cc , v l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +4v i/ov cc _, clk_v cc . . . . . . . . . . . . . . . . . . . . -0.3v to (v cc + 0.3v) i/ov l _, clk_v l , clk_ret. . . . . . . . . . . . . . . -0.3v to (v l + 0.3v) en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +4v short-circuit duration i/ov l _, i/ov cc _, clk_v cc , clk_ret to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . continuous operating conditions operating temperature range . . . . . . . . . . . . . . . . -40c to +85c thermal resistance (typical) ja (c/w) jc (c/w) 14 ld qfn package (notes 4, 5). . . . . 46 6 16 ld tqfn package (notes 4, 5). . . . 74 10 16 ld tqfn package (note 4) . . . . . 93 44 maximum storage temperature range . . . . . . . . . -65c to +150c maximum junction temperature . . . . . . . . . . . . . . . . . . . . . +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a high effective ther mal conductivity test board in free air, and with ?direct attac h? features for the qfn and tqfn. see tech brief tb379 for details. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v cc = +2.2v to +3.6v, v l = +1.35v to +3.2v, en = v l , unless otherwise noted. typical values are at v cc =+3.3v, v l = +1.8v and t a = +25c. (note 6). parameter symbol test conditions temp (c) min (note 8) typ max (note 8) units power supplies v l supply range v l (note 6) full 1.35 - 3.2 v v cc supply range v cc (note 6) full 2.2 - 3.6 v v cc quiescent supply current i cc i/ov cc = v cc , i/ov l = v l full - 18 30 a v l quiescent supply current i vl i/ov cc = v cc , i/ov l = v l full - 12 18 a v cc shutdown supply current i ccsd en = gnd or v l > v cc + 0.7v; ISL3034E and isl3036e only full - - 2.5 a v l > v cc + 0.7v; isl3035e only full - - 2.5 a v l shutdown supply current i lsd en = gnd or v l > v cc + 0.7v; ISL3034E and isl3036e only full - - 4 a v l > v cc + 0.7v; isl3035e only full - - 4 a i/ov cc , clk_v cc tri-state leakage current i lkg v l > v cc + 0.7v, v o = 0v or v cc , isl3035e only full - 0.1 2 a en input current i in_en ISL3034E and isl3036e only full - 1 a v l - v cc shutdown threshold high v th _ h v cc rising full -0.2 0.05v l 0.7 v v l - v cc shutdown threshold low v th_l v cc falling full -0.2 0.1v l 0.7 v i/ov cc , i/ov l pull-up resistance during shutdown r pu_sd1 en = gnd; ISL3034E and isl3036e only full 10 16.5 23 k i/ov l , clk_v l , clk_ret pull-up resistance during shutdown r pu_sd2 v l > (v cc + 0.7v); isl3035e only full 45 75 105 k i/ov l_ , clk_v l , clk_ret pull- up current i vl_pu en = v l , i/ov l = gnd full 20 - 75 a i/ov cc_ , clk_v cc pull-up current i vcc_pu en = v l , i/ov cc = gnd full 20 - 75 a i/ov l to i/ov cc dc resistance r on full - 3 - k ISL3034E, isl3035e, isl3036e
5 fn6492.0 march 31, 2009 esd protection all input and i/o pins from pin to gnd iec61000-4-2 air-gap discharge 25 - 15 - kv iec61000-4-2 contact discharge 25 - > 9 - kv human body model 25 - 15 - kv all pins hbm, per jedec 25 - > 12 - kv machine model, per jedec 25 - 1300 - v logic-level thresholds i/ov l , clk_v l input voltage high threshold v ihl (note 7) full - - v l - 0.2 v i/ov l , clk_v l input voltage low threshold v ill (note 7) full 0.15 - - v i/ov cc , clk_v cc input voltage high threshold v ihc (note 7) full - - v cc - 0.4 v i/ov cc , clk_v cc input voltage low threshold v ilc (note 7) full 0.2 - - v en input voltage high threshold v ih full - - v l - 0.4 v en input voltage low threshold v il full 0.4 - - v i/ov l , clk_ret output voltage high v ohl i oh = 20a, i/ov cc v cc - 0.4v full 2/3 v l --v i/ov l , clk_ret output voltage low v oll i ol = 20a, i/ov cc 0.2v full - - 1/3 v l v i/ov cc , clk_v cc output voltage high v ohc i oh = 20a, i/ov l v l - 0.2v full 2/3 v cc --v i/ov cc , clk_v cc output voltage low v olc i ol = 20a, i/ov l 0.15v full - - 1/3 v cc v rise/fall time accelerator stage accelerator pulse duration on falling edge 25 - 3 - ns on rising edge 25 - 3 - ns i/ov l , clk_ret output accelerator source impedance v l = 1.62v 25 - 11 - v l = 3.2v 25 - 6 - i/ov cc , clk_v cc output accelerator source impedance v cc = 2.2v 25 - 9 - v cc = 3.6v 25 - 8 - i/ov l , clk_ret output accelerator sink impedance v l = 1.62v 25 - 9 - v l = 3.2v 25 - 8 - i/ov cc , clkv cc output accelerator sink impedance v cc = 2.2v 25 - 10 - v cc = 3.6v 25 - 9 - timing characteristics (r source = 150 , input rise/fall time 1ns) i/ov cc , clk_v cc rise time t rvcc r s = 150 , c i/ovcc = 10pf, c clk_vcc = 10pf, push-pull drivers full - - 3.2 ns i/ov cc , clk_v cc fall time t fvcc r s = 150 , c i/ovcc = 10pf, c clk_vcc = 10pf full - - 3.2 ns i/ov l , clk_ret rise time t rvl r s = 150 , c i/ovl = 15pf, c clk_ret = 15pf, push-pull drivers v l 1.35v full - - 4 ns v l 1.62v full - - 3.5 ns electrical specifications v cc = +2.2v to +3.6v, v l = +1.35v to +3.2v, en = v l , unless otherwise noted. typical values are at v cc =+3.3v, v l = +1.8v and t a = +25c. (note 6). (continued) parameter symbol test conditions temp (c) min (note 8) typ max (note 8) units ISL3034E, isl3035e, isl3036e
6 fn6492.0 march 31, 2009 i/ov l , clk_ret fall time t fvl r s = 150 , c i/ovl = 15pf, c clk_ret = 15pf v l 1.35v full - - 4 ns v l 1.62v full - - 3.5 ns i/ov cc , clk_v cc propagation delay (driving i/ov l , clk_v l ) t pdvcc r s = 150 , c i/ovcc = 10pf, c clk_vcc = 10pf, push-pull drivers v l 1.35v full - - 7.5 ns v l 1.62v full - - 6.5 ns t pdvcc channel-to-channel skew (note 9) t skewc v l 1.35v full - - 1.3 ns v l 1.62v full - - 1 ns i/ov l , clk_ret propagation delay (driving i/ov cc , clk_v cc ) t pdvl r s = 150 , c i/ovl = 15pf, c clk_ret =15pf, push-pull drivers full - - 6.5 ns t pdvl channel-to-channel skew (note 9) t skewl v l 1.35v full - - 1.3 ns v l 1.62v full - - 0.8 ns delay from en high to i/ov cc active t en-vcc r load = 1m , c i/ovcc = 10pf (ISL3034E and isl3036e) 25 - 1.5 - s delay from en high to i/ov l active t en-vl r load = 1m , c i/ovl = 15pf (ISL3034E and isl3036e) 25 - 1.5 - s maximum data rate d.r. 1.35 push-pull operation, r source = 150 , c i/ovcc = 10pf, c i/ovl = 15pf, c clk_vcc = 10pf, c clk_ret = 15pf v l 1.35v full 85 - - mbps d.r. 1.6 v l 1.62v full 100 - - mbps notes: 6. v l must be less than or equal to v cc - 0.2v during normal operation. however, v l can be greater than v cc during start-up and shutdown conditions and the part will not latch-up nor be damaged. 7. input thresholds are refe renced to the boost circuit. 8. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. te mperature limits established by characterization and are not production tested. 9. delta between all i/ov l channel prop delays, or delta between all i/ov cc channel prop delays, al l channels tested at the same test conditions. test circuits and waveforms figure 1a. test circuit figure 1b. measurement points figure 1. i/ov cc output propagation delay and transition times (push - pull) electrical specifications v cc = +2.2v to +3.6v, v l = +1.35v to +3.2v, en = v l , unless otherwise noted. typical values are at v cc =+3.3v, v l = +1.8v and t a = +25c. (note 6). (continued) parameter symbol test conditions temp (c) min (note 8) typ max (note 8) units signal generator v l en v cc 150 i/ov l i/ov cc c l v l v l 0v 50% 50% t rvcc 90% 90% t fvcc 10% 10% i/ov l t pdvcc = t plh or t phl 50% 50% t plh t phl v oh v ol i/ov cc ISL3034E, isl3035e, isl3036e
7 fn6492.0 march 31, 2009 figure 2a. test circuit figure 2b. measurement points figure 2. i/ov l output propagation delay and transition times (push - pull) figure 3a. test circuit figure 3b. measurement points figure 3. i/ov cc output enable times figure 4a. test circuit figure 4b. measurement points figure 4. i/ov l output enable times test circuits and waveforms (continued) signal generator v cc en v l 150 i/ov cc i/ov l c l v l v cc 0v 50% 50% t rvl 90% 90% t fvl 10% 10% i/ov cc t pdvl = t plh or t phl 50% 50% t plh t phl v oh v ol i/ov l v cc gnd sw2 parameter sw1 sw2 t enl gnd v cc t enh v cc gnd 1m signal generator v l en v cc i/ov l i/ov cc v cc gnd sw1 v l 0v 50% i/ov cc v cc v ol en output low t enl 50% output high 50% t enh v oh 0v i/ov cc t en-vcc = t enl or t enh v l gnd sw2 parameter sw1 sw2 t enl gnd v l t enh v l gnd 1m signal generator v cc en v l i/ov cc i/ov l v l gnd sw1 v cc 0v 50% i/ov l v l v ol en output low t enl 50% output high 50% t enh v oh 0v i/ov l t en-vl = t enl or t enh ISL3034E, isl3035e, isl3036e
8 fn6492.0 march 31, 2009 application information overview the ISL3034E, isl3035e, isl3036e are 100mbps, bi-directional voltage level translating ics for multi-supply voltage systems. these products shift lower voltage levels on one interface side (supplied by v l ) to a higher voltage level on the other interface side (supplied by v cc ), or vice versa. v oh of the i/ov l pins tracks the v l supply, while v oh of the i/ov cc pins tracks the v cc supply. these ics feature bit-by-bit auto-direction sensing to increase flexibility, and to eliminate the need for direction control pins. on chip pull-up current sources in the active mode, and pull-up resistors in shdn mode, eliminate the need for most external bus resistors. drivers interfacing with these level translators may be open-drain or push-pull types, and all three versions may also be used for unidirectional level shifting. the three versions share the same architecture, but the ISL3034E is a general purpose 6-channel version, while the 6-channel isl3035e specifically targets sd card and other memory card applications. the 4-channel isl3036 targets nibble and byte based applications, as well as 4-wire spi interfaces. power supply ranges allow level shifting between 1.5v, 1.8v, and 2.5v powered devices on the v l side to 2.5v, and 3.3v devices on the v cc side. principles of operation when enabled, these level shifters detect transitions on an i/o pin, and drive the appropriate logic level on the corresponding i/o pin on the other ?side?. if the transition was low-to-high, the channel shifts the voltage up to v cc (for transitions on an i/ov l pin) or down to v l (for transitions on an i/ov cc pin), and then drives the shifted level on the other side. the isl3035e enables whenever v cc > v l + 200mv, while the ISL3034E and isl3036e enable if en = 1 and v cc > v l + 200mv. upon detecting a transition on either i/o pin, that channel?s accelerator circuitry actively drives the opposite side?s (output) pin to gnd or the output ?s supply rail, and then turns off. weak hold circuitry then maintains the logic state until the input is 3-stated, or until another active transition occurs on either i/o pin for that channel. figure 5 shows the simplified block diagram of one level shifting channel. the accelerator circuitry compri ses high and low threshold detectors, one shots with level shifters and large output drivers. a transitio n on one of the i/ov l or i/ov cc pins momentarily defines that pin as an input. when the high or low threshold is crossed, a one-shot fires either the pmos or nmos driver, respectively, on the opposite side (effectively the output). these drivers are large enough to quickly drive the output node to its respective supply or to gnd. note that this transition on the ?output? trips the transition detector on that pin, firing its accelerator, which feeds back to the ?input? to help reinforce slow transitions, such as those from an open-drain type driver. once the one-shot - and thus the accelerator - times out (approximately 3ns to 4ns), the large output drivers tri-state and the pins are weakly held in the last state by the small nmos transistor between i/ov l and i/ov cc (for a low) or by the small current sources (for a high). in this static state, the i/o pins are easily overdriven by the next transition from an external driver. having large pull-up and pull-down devices in the accelerator (vs just an active pull-up) nearly elimin ates the concern about the external driver?s output im pedance, and that impedance?s effect on v ol , fall times and data rate. the weak pull-up current sources on each i/o pin and the nmos pass transistors, remain on whenever the ic is enabled. if a channel?s external driver tri-states, the weak pull-up currents either keep the i/o pins high, or if the last state was a low the current sources pull the i/o pins high. in the latter case, each channel?s accelerators will once again fire when either the i/ov l or the i/ov cc voltage crosses the accelerator?s high threshold level. auto direction sensing each level translator channel independently and automatically determines the di rection of data transfer without any external control si gnals. as described earlier, a transition on either of the channel?s i/o pins momentarily defines that pin as an input, wh ich then translates and drives that input signal to the channel?s corresponding pin on the other port (now the output). after a brief period of active driving, both i/o pins return to their weak ?hold? mode, where the next transition on either i/o pin determines the direction for the next transfer. auto sensing saves valuable processor gpio pins (three [clk, cmd, dat] for sd card applications, or six for the general purpose hex case), and simplifies the software associated with the peripheral interface. using open drain drivers these level translators? accelerator based architecture works equally well when driven by push-pull or open drain type drivers (e.g., for the cm d line initialization in mmc figure 5. one channel simplified schematic i/ov l i/ov cc v cc v l v l en high v th detect low v th detect v cc high v th detect low v th detect # # # # # one-shot and level shifter ISL3034E, isl3035e, isl3036e
9 fn6492.0 march 31, 2009 applications). the low static pull-up current is easily overdriven by an active pull-down, and the feedback nature of the accelerators (i.e., the a ccelerator firing in one direction also triggers the accelerator in the opposite direction) aids the passive pull-up once the input signal passes the accelerator?s high threshold. the pull-up current and load capacitance set the input signal rise time, and thus the maximum data rate. for slow data rates the internal pull-up current may suffice, but higher data rates - or more heavily loaded signal lines - may require an external pull-up resistor. using external bus resistors as mentioned earlier, these level translators incorporate i/o pin pull-up current sources when enabled, and i/o pin pull-up resistors in shdn (exc ept for the isl3035e?s i/ov cc pins). therefore, external pull-up or pull-down resistors shouldn?t be necessary, and aren?t recommended, unless using high-speed open drain signaling. power supplies wide supply range these ics operate from a wide range of supply voltages. v l is designed to connect to the supply of 1.5v, 1.8v, and 2.5v powered devices, while v cc is targeted for 2.5v, and 3.3v components. remember that v cc must be greater than v l for proper operation. power supply sequencing either v cc or v l may be powered up first, but the ic remains in shdn until v cc exceeds v l by as much as 200mv. v l may exceed v cc by as much as 4v without causing any damage. i/o pin input thresholds vs supply voltage even though the ?electrical specification? table on page 4 shows the i/o pin input thresholds (v ih , v il ) with a fixed delta from the supplies or gnd, the thresholds are better represented as a percentage of the supplies. the typical i/ov cc and clk_v cc v ih runs about 55% to 60% of v cc , while the corresponding v il runs about 33% of v cc . the typical i/ov l and clk_v l v ih runs about 60% to 70% of v l , while the corresponding v il runs about 25% to 35% of v l . low power shdn mode this family of level translators features a low power shdn mode that tri-states all the i/o and output pins, considerably reduces current consumption, and enables any pull-up resistors on a port?s i/o pins (see table 1). the ISL3034E and isl3036e enter the shdn mode when the en input switches low, or automatically when the v cc voltage drops below the v l voltage. the isl3035 has no enable pin, so it enters shdn only if v cc drops below v l . the v l supply powers the en circuitry. ISL3034E and isl3036e the ISL3034E and isl3036e are general purpose level translators featuring an enable pin, and six or four channels, respectively. both products include shdn mode 16.5k pull-ups on the i/ov cc and i/ov l pins. isl3035e the isl3035e specifically targets memory card applications, and figure 6 illustrates its use in an sd card application. instead of six general purpose channels, the isl3035e features five general purpose channels and one dedicated clk channel. in memory card applications, the clk channel is a unidirectional signal driv en by the host controller and used by the memory card to synchronize data reads and writes. the isl3035e?s clk cha nnel is unique in that the host clk applied to the clk_v l pin routes to the memory card via the clk_v cc pin, but it also loops back to the host on the clk_ret pin. this clk_ret signal better mimics the timing of ?read? data returned from the memory card (see figure 21 for signal timing), so using clk_ret as the host?s input clk improves the clk to data timing relationship. clk_ret is strictly an output, and clk_v l is strictly an input. if an isl3035e application needs a sixth i/o channel then the user needs to connect clk_v l and clk_ret together. connected this way, the combination channel has the same architecture as the other i/o channels. both clk_ret and clk_v l have equivalent pull-up current sources and shdn pull-up resistors, so connec ting these two pins together doubles the pull-up current in either mode. the bit-by-bit auto direction co ntrol eliminates the need for gpio signals to control the flow of data on the cmd and dat lines. the isl3035e has no enable pin, so it only enters the low power shdn mode when v cc drops below v l . there are no shdn pull-up resistors on the i/ov cc and clk_v cc pins, but there are 75k pull-ups on the i/ov l , clk_v l , and clk_ret pins. figure 6. isl3035e in an sd card application v l v cc i/ov l_ i/ov l_ isl3035e clk_ret i/ov l_ i/ov l_ i/ov l_ gnd i/ov cc_ i/ov cc_ i/ov cc_ i/ov cc_ i/ov cc_ clk_v l clk_v cc dat3 dat2 dat1 dat0 cmd clock gnd gnd +3.3v sd card dat3 dat2 clock_in dat1 dat0 cmd clock +1.8v system controller 0.1 f 0.1 f +1.8v 1 f +3.3v host 1 f ISL3034E, isl3035e, isl3036e
10 fn6492.0 march 31, 2009 best-in-class esd protection all pins on these devices in clude class 3 (>12kv) human body model (hbm) esd protecti on structures, but the input and i/o pins incorporate advanced structures allowing them to survive esd events in excess of 15kv hbm and 15kv to iec61000-4-2. the i/ov cc pins are particularly vulnerable to esd damage because they typically connect to an exposed port on the ex terior of the finished product. simply touching the port pi ns, or connecting a memory card, can cause an esd event that might destroy unprotected ics. these new esd structures protect the device whether or not it is powered up and without degrading the level shifting performance. this built-in esd protection eliminates the ne ed for board level protection structures (e.g., transient suppression diodes) and the associated, undesirable capacitive load they present. to ensure the full benefit of the built-in esd protection, connect the ic?s gnd pin directly to a low impedance gnd plane. iec61000-4-2 testing the iec61000 test method applies to finished equipment, rather than to an individual ic. therefore, the pins most likely to suffer an esd event are t hose that are exposed to the outside world (typically i/ov cc pins in memory card applications) but the ISL3034E, isl3035e, and isl3036e feature iec61000 esd protection on all logic and i/o pins (both i/ov l and i/ov cc , as well as clk pins). unlike hbm and mm methods which only test each pin-to-pin combination without applying power, iec61000 testing is also performed with the ic in its typical application configuration (power applied). the iec61000 standard?s lower current limiting resistor coupled with the larger charge storage capacitor yields a test that is much more severe than the hbm test. the extra esd protection built into these devices? pins allows the desi gn of equipment meeting level 4 criteria without the need for a dditional board level protection. air-gap discharge test method for this test method, a charged probe tip moves toward the ic pin until the voltage arcs to it. the current waveform delivered to the ic pin depends on approach speed, humidity, temperature, etc., so it is difficult to obtain repeatable results. all the en, clk, and i/o pins withstand 15kv air-gap discharges, relative to gnd. contact discharge test method during the contact discharge test, the probe contacts the tested pin before the probe tip is energized, thereby eliminating the variables associated with the air-gap discharge. the result is a more repeatable and predictable test, but equipment limits prevent testing devices at voltages higher than 9kv. devices in this family survive 9kv contact discharges (relative to the gnd pin) on the en, clk, and i/o pins. layout and decoupling considerations these level translators? high data rates and fast signal transitions require that the accelerators have high transient currents. thus, short, low inductance supply traces and decoupling within 1/8th inch of the ic are imperative with very low impedance gnd return paths. typical performance curves v cc = 3.3v, v l = 1.8v, c l = 15pf, r source = 150 , data rate = 100mbps, push-pull driver, t a = +25c; unless otherwise specified. figure 7. v l supply current vs v cc supply voltage figure 8. v l supply current vs v l supply voltage v cc supply voltage (v) v l supply current (ma) 0 0.5 1.0 1.5 2.0 2.5 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v l = 1.8v switching 6 i/ov l inputs switching 1 i/ov l input switching 4 i/ov l inputs v l supply voltage (v) v l supply current (ma) 0 5 10 15 20 25 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 v cc = 3.6v switching 6 i/ov cc inputs 3.2 switching 4 i/ov cc inputs switching 1 i/ov cc input ISL3034E, isl3035e, isl3036e
11 fn6492.0 march 31, 2009 figure 9. v cc supply current vs v cc supply voltage figure 10. v cc supply current vs v l supply voltage figure 11. supply current vs temperature figure 12. supply current vs temperature figure 13. v l supply current vs i/ ov l capacitive load figure 14. v cc supply current vs i/ ov cc capacitive load typical performance curves v cc = 3.3v, v l = 1.8v, c l = 15pf, r source = 150 , data rate = 100mbps, push-pull driver, t a = +25c; unless otherwise specified. (continued) v cc supply voltage (v) v cc supply current (ma) 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 0 5 10 15 20 25 30 35 v l = 1.8v switching 6 i/ov l inputs switching 1 i/ov l input switching 4 i/ov l inputs v l supply voltage (v) v cc supply current (ma) 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.2 0 2 4 6 8 10 12 14 16 v cc = 3.6v switching 6 i/ov cc inputs switching 4 i/ov cc inputs switching 1 i/ov cc input temperature (c) supply current (ma) 2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 -40 -15 10 35 60 85 i cc i l switching 1 i/ov cc input temperature (c) supply current (ma) -40 -15 10 35 60 85 0 1 2 3 4 5 6 7 i cc i l switching 1 i/ov l input capacitive load (pf) v l supply current (ma) 0 2 4 6 8 10 12 14 16 18 10 15 20 25 30 35 switching 6 i/ov cc inputs switching 4 i/ov cc inputs switching 1 i/ov cc input capacitive load (pf) v cc supply current (ma) 10 15 20 25 30 35 0 5 10 15 20 25 30 35 40 switching 6 i/ov l inputs switching 1 i/ov l input switching 4 i/ov l inputs ISL3034E, isl3035e, isl3036e
12 fn6492.0 march 31, 2009 figure 15. rise/fall time vs i/ ov cc capacitive load figure 16. rise/fall time vs i/ ov l capacitive load figure 17. propagation delay vs i/ ov cc capacitive load figure 18. propagation delay vs i/ ov l capacitive load figure 19. i/ov cc output waveforms (100mbps) figure 20. i/ov l output waveforms (100mbps) typical performance curves v cc = 3.3v, v l = 1.8v, c l = 15pf, r source = 150 , data rate = 100mbps, push-pull driver, t a = +25c; unless otherwise specified. (continued) capacitive load (pf) rise and fall times (ns) 10 15 20 25 30 35 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 t rvcc t fvcc switching i/ov l input capacitive load (pf) rise and fall times (ns) 10 15 20 25 30 35 0.9 1.1 1.3 1.5 1.7 1.9 2.1 t rvl t fvl switching i/ov cc input capacitive load (pf) propagation delay (ns) 10 15 20 25 30 35 3.0 3.2 3.4 3.6 3.8 4.0 4.2 t plh t phl switching i/ov l input capacitive load (pf) propagation delay (ns) 10 15 20 25 30 35 2.4 2.6 2.8 3.0 3.2 3.4 t plh t phl t plh switching i/ov cc input time (4ns/div) i/ov l input (v) i/ov cc output (v) 0 0.5 1.0 1.5 2.0 0 0.5 1.0 1.5 2.0 2.5 3.0 c l = 35pf 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 time (4ns/div) i/ov cc input (v) i/ov l output (v) 0 0.5 1.0 1.5 2.0 c l = 15pf ISL3034E, isl3035e, isl3036e
13 fn6492.0 march 31, 2009 figure 21. isl3035e clock waveforms (100mbps) die characteristics substrate and tqfn/qfn thermal pad potential (powered up): gnd transistor count: ISL3034E, isl3035e - 2600 isl3036e - 2000 process: si gate bicmos typical performance curves v cc = 3.3v, v l = 1.8v, c l = 15pf, r source = 150 , data rate = 100mbps, push-pull driver, t a = +25c; unless otherwise specified. (continued) time (4ns/div) clk_v l input (v) clk_ret output (v) clk_v cc output (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 2.0 c l = 15pf c l = 35pf 0 1 2 ISL3034E, isl3035e, isl3036e
14 fn6492.0 march 31, 2009 ultra thin quad flat no-lead plastic package (utqfn) 6 b e a d 0.10 c 2x c 0.05 c a 0.10 c a1 seating plane index area 2 1 n top view bottom view side view nx (b) section "c-c" e cc 5 c l terminal tip (a1) l 0.10 c 2x e l1 nx l 2 1 0.10 m c a b 0.05 m c 5 nx b (datum b) (datum a) pin #1 id 16x 3.00 1.40 2.20 0.40 0.50 0.20 0.40 0.20 0.90 1.40 1.80 land pattern 10 k l16.2.6x1.8a 16 lead ultra thin quad flat no-lead plastic package symbol millimeters notes min nominal max a 0.45 0.50 0.55 - a1 - - 0.05 - a3 0.127 ref - b 0.15 0.20 0.25 5 d 2.55 2.60 2.65 - e 1.75 1.80 1.85 - e 0.40 bsc - k0.15 - - - l 0.35 0.40 0.45 - l1 0.45 0.50 0.55 - n162 nd 4 3 ne 4 3 0- 12 4 rev. 5 2/09 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on d and e side, respectively. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. maximum package warpage is 0.05mm. 8. maximum allowable burrs is 0.076mm in all directions. 9. jedec reference mo-255. 10. for additional information, to assist with the pcb land pattern design effort, see intersil technical brief tb389. ISL3034E, isl3035e, isl3036e
15 fn6492.0 march 31, 2009 package outline drawing l14.3.5x3.5 14 lead quad dual flat no-lead plastic package (qfn) rev 0, 2/08 bottom view top view side view detail ?x? typical recommended land pattern pin #1 index area 6 2 1 14 0 . 00 min. 0 . 05 max. 5 0 . 2 ref c (4x) 0.15 index area 6 pin 1 3.50 b a 3.50 8x 0.50 2x 2.0 6 7 8 9 13 a + 0.07 14x 0.40 0.10 4 16x 0.23 mc 0.10 - 0.05 b 2.05 0 . 15 2x 1.50 0 . 90 0.1 see detail "x" c 0.10 base plane 0.08 seating plane c c ( 2.05) ( 14 x 0.60) ( 14x 0.23 ) ( 2x 1.5 ) ( 2.00 ) ( 3.30 typ ) (8x 0.50) view ?a-a? located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be measured between 0.15mm and 0.30mm from the terminal tip. lead width dimension applies to the metallized terminal and is dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: ISL3034E, isl3035e, isl3036e
16 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com thin quad flat no-lead plastic package (tqfn) thin micro lead frame pl astic package (tmlfp) ) index d1/2 d1 d/2 d e1/2 e/2 e a 2x 0.15 b c 0.10 b a mc a n seating plane n 6 3 2 2 3 e 1 1 0.08 for odd terminal/side for even terminal/side c c section "c-c" nx b a1 c 2x c 0.15 0.15 2x b 0 ref. (nd-1)xe (ne-1)xe ref. 5 a1 4x p a c c 4x p b 2x a c 0.15 a2 a3 d2 d2 e2 e2/2 terminal tip side view top view 7 bottom view 7 5 c l c l e e e1 2 nx k nx b 8 nx l 8 8 9 area 9 4x 0.10 c / / 9 (datum b) (datum a) area index 6 area n 9 corner option 4x l1 l 10 l1 l 10 l16.3x3a 16 lead thin quad flat no-lead plastic package symbol millimeters notes min nominal max a 0.70 0.75 0.80 - a1 - - 0.05 - a2 - - 0.80 9 a3 0.20 ref 9 b 0.18 0.23 0.30 5, 8 d 3.00 bsc - d1 2.75 bsc 9 d2 1.35 1.50 1.65 7, 8, 10 e 3.00 bsc - e1 2.75 bsc 9 e2 1.35 1.50 1.65 7, 8, 10 e 0.50 bsc - k0.20 - - - l 0.30 0.40 0.50 8 n162 nd 4 3 ne 4 3 p- -0.609 --129 rev. 0 6/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are prov ided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. compliant to jedec mo-220weed-2 issue c, except for the e2 and d2 max dimension. ISL3034E, isl3035e, isl3036e

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